system verilog - Systemverilog property implication with or (||) is not working as expected? -

i trying write sytemverilog assertions determining clock period(140mhz) arbitrary + or - value of 0.001ns, here in systemverilog property used "or" operator (||) +/- deviations/changes of time periods outputs not expected, can explain exact cause of this?, , value of clk_prd assertion gets asserted not expected, please mention optimal solution this?

code snippet below,

module clock_gen();     timeunit 1ns;     timeprecision 100ps;       bit clk;     realtime clk_prd =1000/340.0ns; //2.9411764     //realtime clk_prd =1000/140.0ns; //7.1428571     property sva_clk(real clk_prd);       time current_time;       (('1,current_time=$realtime) |=>          (clk_prd <= $realtime-(current_time - 0.001ns)) ||         (clk_prd >= $realtime-(current_time + 0.001ns)));      endproperty      assert_period:assert property (@(posedge clk)sva_clk(clk_prd))       $display("clk pass : %0t ",$realtime);      else       $warning("clk fail : %0t",$realtime);     initial forever #7.1428 clk=!clk;      initial begin        repeat(15) @(posedge clk);        $finish;      end     endmodule : clock_gen 

current output:

clk pass : 213  clk pass : 355  clk pass : 497  clk pass : 639  clk pass : 781  clk pass : 923  clk pass : 1065  clk pass : 1207  clk pass : 1349  clk pass : 1491  clk pass : 1633  clk pass : 1775  clk pass : 1917  

expected output

clk fail : 213  clk fail : 355  clk fail : 497  clk fail : 639  clk fail : 781  clk fail : 923  clk fail : 1065  clk fail : 1207  clk fail : 1349  clk fail : 1491  clk fail : 1633  clk fail : 1775  clk fail : 1917   

(ref link)

there multitude problems code

1. the timeprecision should in 1ps code written
2. current_time should declared realtime
3. your clock generator period 14.2, should have written #(7.1428ns/2)
4. you either have +/- reversed , or <=/>= reversed.